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19-5781; Rev 0; 3/11
KIT ATION EVALU LE B AVAILA
36V, 1MHz Step-Down Controller with Low Operating Current
General Description Features
Wide 3.5V to 36V Input Voltage Range 42V Input Transient Tolerance High Duty Cycle During Undervoltage Transients 220kHz to 1MHz Adjustable Switching Frequency Current-Mode Control Architecture Adjustable (1V to 13V) Output Voltage with 2% Accuracy Three Operating Modes 50A Ultra-Low Quiescent Current Skip Mode Forced Fixed-Frequency Mode External Frequency Synchronization Lowest BOM Count, Current-Mode Control Architecture Power-Good Output Enable Input Compatible from 3.3V Logic Level to 42V Current-Limit, Thermal Shutdown, and Overvoltage Protection -40C to +125C Automotive Temperature Range Automotive Qualified
MAX16955
The MAX16955 is a current-mode, synchronous PWM step-down controller designed to operate with input voltages from 3.5V to 36V while using only 50A of quiescent current at no load. The switching frequency is adjustable from 220kHz to 1MHz by an external resistor and can be synchronized to an external clock up to 1.1MHz. The MAX16955 output voltage is pin programmable to be either 5V fixed, or adjustable from 1V to 13V. The wide input voltage range, along with its ability to operate in dropout during undervoltage transients, makes it ideal for automotive and industrial applications. The MAX16955 operates in fixed-frequency PWM mode and low quiescent current skip mode. It features an enable logic input, which is compatible up to 42V to disable the device and reduce its shutdown current to 10A. Protection features include overcurrent limit, overvoltage, undervoltage, and thermal shutdown with automatic recovery. The device also features a powergood monitor to ease power-supply sequencing. The MAX16955 is available in a thermally enhanced 16pin TSSOP package with exposed pad and is specified for operation over the -40C to +125C automotive temperature range.

Typical Operating Circuit
VBAT CIN SUP DH BST LX CBST L NH
Applications
Automotive Industrial Military Point of Load
RCOMP CCOMP2 COMP
Ordering Information
PART MAX16955AUE/V+ TEMP RANGE -40C to +125C PIN-PACKAGE 16 TSSOP-EP*
CCOMP1
MAX16955
PGOOD EN FSYNC FOSC RFOSC SGND
DL PGND CS OUT FB BIAS CL
NL
RSENSE
/V denotes an automotive qualified part. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
VOUT 5V COUT
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
36V, 1MHz Step-Down Controller with Low Operating Current MAX16955
ABSOLUTE MAXIMUM RATINGS
SUP and EN to SGND ............................................-0.3V to +42V LX to PGND ..............................................................-1V to +42V BST to LX .................................................................-0.3V to +6V BIAS, FB, PGOOD, FSYNC to SGND .......................-0.3V to +6V DH to LX ...................................................................-0.3V to +6V DL to PGND .............................................-0.3V to (VBIAS + 0.3V) FOSC to SGND ........................................-0.3V to (VBIAS + 0.3V) CS and OUT to SGND .........................................-0.3V to +12.7V *As per JEDEC51 standard (multilayer board).
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PGND to SGND .....................................................-0.3V to +0.3V Continuous Power Dissipation (TA = +70C) TSSOP (derate 26.1mW/C above +70C) .............2088.8mW* Operating Temperature Range .........................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) .......................................+260C
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP Junction-to-Ambient Thermal Resistance (JA) .........38.3C/W Junction-to-Case Thermal Resistance (JC) ...................3C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VSUP = VEN = 14V, CIN = 10F, COUT = 94F, CBIAS = 2.2F, CBST = 0.1F, RFOSC = 76.8k, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER SUP Input Voltage Range SUP Operating Supply Current Skip Mode Supply Current SUP Shutdown Supply Current BIAS Voltage BIAS Undervoltage Lockout BIAS Undervoltage Lockout Hysteresis BIAS Minimum Load OUTPUT VOLTAGE (OUT) Output Voltage Adjustable Range OUT Pulldown Resistance Output Voltage (5V Fixed Mode) FB Feedback Voltage (Adjustable Mode) FB Current RPULL_D VOUT VFB IFB VEN = 0V or fault condition active VSUP = 6V to 36V, VFB = VBIAS, fixedfrequency mode (Note 4) VSUP = 6V to 36V, 0V < (VCS - VOUT) < 80mV, fixed-frequency mode VFB = 1.0V 4.925 0.99 1.0 30 5.0 1.0 0.02 5.075 1.01 V V A 13 V IBIAS(MIN) SYMBOL VSUP I SUP I SKIP I SHDN,SUP VBIAS VUVBIAS (Note 3) Fixed 5V output, fixed-frequency, PWM mode, VFB = VBIAS, no external FETs connected No load, fixed 5V output VEN = 0V VSUP = 3.5V, IBIAS = 45mA 6V < VSUP < 36V VBIAS rising VBIAS falling VSUP - VBIAS > 200mV 4.7 CONDITIONS MIN 3.5 1 50 10 3.0 5.0 3.1 200 45 5.3 3.4 90 20 TYP MAX 36 UNITS V mA A A V V mV mA
2
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36V, 1MHz Step-Down Controller with Low Operating Current
ELECTRICAL CHARACTERISTICS (continued)
(VSUP = VEN = 14V, CIN = 10F, COUT = 94F, CBIAS = 2.2F, CBST = 0.1F, RFOSC = 76.8k, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER FB Line Regulation Transconductance (from FB to COMP) Error-Amplifier Output Impedance Operating Frequency Minimum On-Time Maximum FSYNC Frequency Minimum FSYNC Frequency FSYNC Switching Threshold High FSYNC Switching Threshold Low FSYNC Internal Pulldown Resistance CURRENT LIMIT CS Input Current Output Input Current CS Current-Limit Voltage Threshold FAULT DETECTION Output Overvoltage Trip Threshold Output Overvoltage Trip Hysteresis Output Overvoltage Fault Propagation Delay Output Undervoltage Trip Threshold Output Undervoltage Trip Hysteresis Output Undervoltage Propagation Delay PGOOD Output Low Voltage PGOOD Leakage Current Thermal Shutdown Threshold Thermal Shutdown Hysteresis VPGOOD,L I PGOOD TSHDN (Note 5) (Note 5) Falling edge Rising edge (excluding startup) I SINK = 3mA 1 +175 15 t OVP VFB,UV Rising edge Falling edge VOUT = VFB; with respect to slewed FB threshold, falling edge 83 VFB,OV VOUT = VFB, rising edge 108 113 2.5 25 25 88 2.5 25 25 0.4 93 118 %VFB % s %VFB % s V A C C ICS I OUT VLIMIT VCS = V OUT = 0V or VBIAS (Note 4) During normal operation VFB = VBIAS VCS - VOUT, VBIAS = 5V, VOUT 2.5V 68 -1 22 32 80 92 +1 A A mV gm,EA R OUT,EA f SW t ON(MIN) fFSYNC(MAX) fFSYNC(MIN) VFSYNC,HI VFSYNC,LO 1 fFSYNC > 110% of internal frequency (20% duty cycle), f SW = 220kHz 1.4 0.4 RFOSC = 76.8k RFOSC = 30.1k 360 SYMBOL CONDITIONS VEN = V SUP, 6V < VSUP < 36V (Note 4) MIN TYP 0.02 1200 30 400 1000 80 1100 242 440 MAX UNITS %/V S M kHz ns kHz kHz V V M
MAX16955
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36V, 1MHz Step-Down Controller with Low Operating Current MAX16955
ELECTRICAL CHARACTERISTICS (continued)
(VSUP = VEN = 14V, CIN = 10F, COUT = 94F, CBIAS = 2.2F, CBST = 0.1F, RFOSC = 76.8k, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER GATE DRIVE DH Gate-Driver On-Resistance DL Gate-Driver On-Resistance DH/DL Dead Time (Note 4) BST Input Current BST On-Resistance ENABLE INPUT EN Input Threshold Low EN Input Threshold High EN Threshold Voltage Hysteresis EN Input Current SOFT-START Soft-Start Ramp Time t SS 5 ms I EN VEN,LO VEN,HI 2.2 0.2 0.5 1.2 V V V A RDH RDL tDEAD IBST (VBST - VLX) forced to 5V (VBST - VLX) forced to 0V DL = high state DL = low state DL rising (Note 5) DH rising (Note 5) VLX = 0V, VBST = 5V, VDH - VLX = VDL - VPGND = 0V (Note 5) 10 2 3.5 2 60 60 1 5 15 ns A SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 2: Note 3: Note 4: Note 5:
Devices tested at TA = +25C. Limits over temperature are guaranteed by design. For 3.5V operation, the n-channel MOSFET's threshold voltage should be compatible to (lower than) this input voltage. Device not in dropout condition. Guaranteed by design; not production tested.
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36V, 1MHz Step-Down Controller with Low Operating Current
Typical Operating Characteristics
(VSUP = VEN = 14V, CIN = 10F, COUT = 94F, CBIAS = 2.2F, CBST = 0.1F, RFOSC = 66.5k, fOSC = 468kHz, VFB = VBIAS, VOUT = 5V, TA = +25C, unless otherwise noted.)
VOUT = 3.3V STARTUP RESPONSE (SKIP MODE) VOUT = 5V STARTUP RESPONSE (SKIP MODE)
10V/div VOUT 2V/div
MAX16955
MAX16955 toc01
MAX16955 toc02
10V/div VOUT 2V/div
IOUT 2A/div
IOUT 2A/div
5V/div VPGOOD 2ms 2ms
5V/div VPGOOD
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX16955 toc03
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX16955 toc04
EFFICIENCY vs. LOAD CURRENT
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 FIXED-FREQUENCY MODE 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 LOAD CURRENT (A) VOUT = 5V VOUT = 3.3V
MAX16955 toc05
40 35 SUPPLY CURRENT (mA) 30 25 20 15 10 5 0 6
100 90 80 SUPPLY CURRENT (A) 70 60 50 40 30 20 10 0
FIXED-FREQUENCY MODE
SKIP MODE
100
12
18
24
30
36
6
12
18
24
30
36
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
EFFICIENCY vs. LOAD CURRENT
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.0001
SKIP MODE
MAX16955 toc06
SWITCHING FREQUENCY vs. RFOSC
1200 1150 1100 1050 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 RFOSC (kI)
MAX16955 toc07
100
VOUT = 5V
FREQUENCY (kHz) 10
VOUT = 3.3V
0.001
0.01
0.1
1
25 35 45 55 65 75 85 95 105 115 125 135 145
LOAD CURRENT (A)
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5
36V, 1MHz Step-Down Controller with Low Operating Current MAX16955
Typical Operating Characteristics (continued)
(VSUP = VEN = 14V, CIN = 10F, COUT = 94F, CBIAS = 2.2F, CBST = 0.1F, RFOSC = 66.5k, fOSC = 468kHz, VFB = VBIAS, VOUT = 5V, TA = +25C, unless otherwise noted.)
0 TO 4A LOAD-TRANSIENT RESPONSE, VOUT = 5V, PWM MODE 0 TO 4A LOAD-TRANSIENT RESPONSE, VOUT = 3.3V, PWM MODE SYNCHRONIZATION WITH EXTERNAL CLOCK fFSYNC = 1MHz
MAX16955 toc10
MAX16955 toc08
MAX16955 toc09
IOUT 2A/div
IOUT 2A/div
VFSYNC 2V/div
VOUT 200mV/div
VOUT 200mV/div
VLX 5V/div
100s
100s
1s
COLD CRANK (PWM MODE)
MAX16955 toc11
LOAD DUMP RESPONSE (SKIP MODE)
VSUP 5V/div
MAX16955 toc12
LOAD DUMP RESPONSE (PWM MODE)
VSUP 20V/div
MAX16955 toc13
VSUP 20V/div
VOUT 5V/div ILX 5A/div VPGOOD 5V/div 10ms 100ms
VOUT 5V/div ILX 5A/div VPGOOD 5V/div 100ms
VOUT 5V/div ILX 5A/div VPGOOD 5V/div
SLOW INPUT RESPONSE (PWM MODE)
MAX16955 toc14
SLOW INPUT RESPONSE (SKIP MODE)
VSUP 10V/div
MAX16955 toc15
VSUP 10V/div
VLX 10V/div VOUT 5V/div VPGOOD 5V/div 10s 10s
VLX 10V/div VOUT 5V/div VPGOOD 5V/div
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36V, 1MHz Step-Down Controller with Low Operating Current MAX16955
Typical Operating Characteristics (continued)
(VSUP = VEN = 14V, CIN = 10F, COUT = 94F, CBIAS = 2.2F, CBST = 0.1F, RFOSC = 66.5k, fOSC = 468kHz, VFB = VBIAS, VOUT = 5V, TA = +25C, unless otherwise noted.)
SHORT-CIRCUIT RESPONSE, VOUT = 5V
MAX16955 toc16
SHORT-CIRCUIT RESPONSE, VOUT = 3.3V
MAX16955 toc17
VOUT 2V/div
VOUT 2V/div
IOUT 5A/div
IOUT 5A/div
VPGOOD 5V/div
VPGOOD 5V/div
400s
400s
LOAD REGULATION
MAX16955 toc18
LOAD REGULATION
4 3 2 ERROR (%) 1 0 -1 -2 -3 -4 -5 TA = +25C TA = -40C SKIP MODE
MAX16955 toc19
OUTPUT-VOLTAGE ERROR vs. TEMPERATURE
4 3 2 ERROR (%) 1 0 -1 -2 FIXED-FREQUENCY MODE -3 -4 -5 SKIP MODE
MAX16955 toc20
5 4 3 2 ERROR (%) 1 0 -1 -2 -3 -4 -5 0
FIXED-FREQUENCY MODE
5
5
TA = +25C
TA = -40C
TA = +125C
TA = +125C
1
2 LOAD CURRENT (A)
3
4
0
1
2 LOAD CURRENT (A)
3
4
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
LINE REGULATION
3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 6 FIXED-FREQUENCY MODE 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 6
MAX16955 toc21
LINE REGULATION
SKIP MODE
MAX16955 toc22
BIAS VOLTAGE vs. BIAS CURRENT
4 BIAS VOLTAGE ERROR (%) 3 2 1 0 -1 -2 -3 -4 -5 TA = +25C TA = +125C 0 20 40 60 80 100 TA = -40C
MAX16955 toc23
5
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TA = +25C
TA = -40C
TA = +25C
TA = -40C
TA = +125C
TA = +125C
12
18
24
30
36
12
18
24
30
36
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
BIAS CURRENT (mA)
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36V, 1MHz Step-Down Controller with Low Operating Current MAX16955
Typical Operating Characteristics (continued)
(VSUP = VEN = 14V, CIN = 10F, COUT = 94F, CBIAS = 2.2F, CBST = 0.1F, RFOSC = 66.5k, fOSC = 468kHz, VFB = VBIAS, VOUT = 5V, TA = +25C, unless otherwise noted.)
SHUTDOWN CURRENT vs. VSUP
MAX16955 toc24
SHUTDOWN CURRENT vs. TEMPERATURE
VSUP = 14V VEN = 0V
MAX16955 toc25
SWITCHING FREQUENCY vs. LOAD CURRENT
0.8 0.6 FREQUENCY (kHz) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX16955 toc26
20 18 SHUTDOWN CURRENT (A) 16 14 12 10 8 6 4 2 0 3 6
10.60 10.55 SHUTDOWN CURRENT (A) 10.50 10.45 10.40 10.35 10.30
1.0
9 12 15 18 21 24 27 30 33 36 VSUP (V)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C )
0
1
2 LOAD CURRENT (A)
3
4
DIPS AND DROPS TEST, PWM MODE, VOUT = 5V
MAX16955 toc27
DIPS AND DROPS TEST, SKIP MODE, VOUT = 5V
VSUP 10V/div VLX 10V/div VOUT 2V/div
MAX16955 toc28
VSUP 10V/div VLX 10V/div VOUT 2V/div
VPGOOD 5V/div 10ms 10ms
VPGOOD 5V/div
DIPS AND DROPS TEST, PWM MODE, VOUT = 3.3V
MAX16955 toc29
DIPS AND DROPS TEST, SKIP MODE, VOUT = 3.3V
VSUP 10V/div VLX 10V/div VOUT 2V/div
MAX16955 toc30
VSUP 10V/div VLX 10V/div VOUT 2V/div
VPGOOD 5V/div 10ms 10ms
VPGOOD 5V/div
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36V, 1MHz Step-Down Controller with Low Operating Current
Pin Configuration
TOP VIEW
MAX16955
SUP EN FOSC FSYNC SGND COMP FB CS
1 2 3
+
16 15 14
BST DH LX BIAS DL PGND PGOOD OUT
MAX16955
4 5 6 7 EP 8 9 13 12 11 10
TSSOP
Pin Description
PIN 1 NAME SUP FUNCTION Input Supply Voltage. SUP is the input voltage to the internal linear regulator. Bypass SUP to PGND with a 1F minimum value ceramic capacitor. Connect BIAS and SUP to a 5V rail, if available. Active-High Enable Input. EN is compatible with 5V and 3.3V logic levels. Drive EN logic-high to enable the output or drive EN logic-low to put the controller in low-power shutdown mode. Connect EN to SUP for always-on operation. Do not leave EN unconnected. Oscillator-Timing Resistor Input. Connect a resistor from FOSC to SGND to set the oscillator frequency from 220kHz to 1MHz. See the Setting the Switching Frequency section. Synchronization and Mode Selection Input. Connect FSYNC to BIAS to select fixed-frequency PWM mode and disable skip mode. Connect FSYNC to SGND to select skip mode. Connect FSYNC to an external clock for synchronization. FSYNC is internally pulled down to ground with a 1M resistor. Signal Ground. Connect SGND directly to the local ground plane. Connect SGND to PGND at a single point, typically near the output capacitor return terminal. Error Amplifier Output. Connect COMP to the compensation feedback network. See the Compensation Design section. Feedback Regulation Point. Connect FB to BIAS for a fixed 5V output voltage. In adjustable mode, connect to the center tap of a resistive divider from the output (VOUT) to SGND to set the output voltage. The FB voltage regulates to 1V (typ). Positive Current-Sense Input. Connect CS to the positive terminal of the current-sense element. Figure 4 shows two different current-sensing options: 1) accurate sense with a sense resistor or 2) lossless inductor DCR sensing. Output Sense and Negative Current-Sense Input. When using the internal preset 5V feedback divider (FB = BIAS), the controller uses OUT to sense the output voltage. Connect OUT to the negative terminal of the current-sense element.
2
EN
3
FOSC
4
FSYNC
5 6
SGND COMP
7
FB
8
CS
9
OUT
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36V, 1MHz Step-Down Controller with Low Operating Current MAX16955
Pin Description (continued)
PIN 10 NAME PGOOD FUNCTION Open-Drain Power-Good Output. A logic-high voltage on PGOOD indicates that the output voltage is in regulation. PGOOD is pulled low when the output voltage is out of regulation. Connect a 10k pullup resistor from PGOOD to the digital interface voltage. Power Ground. Connect the input and output filter capacitors' negative terminals to PGND. Connect PGND externally to SGND at a single point, typically at the output capacitor return terminal. Low-Side Gate-Driver Output. DL swings from VBIAS to PGND. To avoid any interference with the internal break-before-make circuitry, do not connect any resistor between DL and the gate of the MOSFET. Internal 5V Linear Regulator Output. BIAS provides power for bias and gate drive. Connect a 1F to 10F ceramic capacitor from BIAS to PGND. Connect BIAS and SUP to a 5V rail, if available. External Inductor Connection. Connect LX to the switched side of the inductor. LX serves as the lower supply rail for the DH high-side gate driver. High-Side Gate-Driver Output. DH swings from LX to BST. To avoid any interference with the internal break-before-make circuitry, do not connect any resistor between DH and the gate of the MOSFET. Boost Flying Capacitor Connection. Connect a ceramic capacitor between BST and LX. See the BoostFlying Capacitor Selection section for details. Exposed Pad. Internally connected to ground. Connect EP to a large contiguous copper plane at SGND potential to improve thermal dissipation. Do not use as the main ground connection.
11 12 13 14 15 16 --
PGND DL BIAS LX DH BST EP
10
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36V, 1MHz Step-Down Controller with Low Operating Current
Functional Diagram
MAX16955
SUP
BST
EN
EN LDO
MAX16955
BST SWITCH
UG
DH
SGND LX
PGOOD FB REF BIAS
BUCK CONTROLLER
BIAS
LG PWM EAFB COMP EA REF ILIM
DL
PGND
OSC FOSC
CLK CS ZX
FSYNC
MODE SYNC
MODE
CS
OUT
FBI
SGND
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11
36V, 1MHz Step-Down Controller with Low Operating Current MAX16955
Detailed Description
The MAX16955 is a current-mode, synchronous PWM buck controller designed to drive logic-level MOSFETs. The device tolerates a wide 3.5V to 42V input voltage range and generates an adjustable 1V to 13V or fixed 5V output voltage. This device can operate in dropout mode, making it ideal for automotive and industrial applications with undervoltage transients. The internal switching frequency is adjustable from 220kHz to 1MHz with an external resistor and can be synchronized to an external clock. The high switching frequency reduces output ripple and allows the use of small external components. The device operates in both fixed-frequency PWM mode and a low quiescent current skip mode. While working in skip mode, the operating current is as low as 50A. The device features an enable logic input to disable the device and reduce its shutdown current to 10A. Protection features include cycle-by-cycle current limit, overvoltage detection, and thermal shutdown. The device also features integrated soft-start and a powergood monitor to help with power sequencing. (max), the controller starts up with a 5ms fixed soft-start time. Once regulation is reached, PGOOD goes high impedance. A logic-low at EN shuts down the device. During shutdown, the internal linear regulator and gate drivers turn off. Shutdown is the lowest power state and reduces the quiescent current to 10A (typ). To protect the low-side MOSFET during shutdown, the step-down regulator cannot be enabled until the output voltage drops below 1.25V. An internal 30 pulldown switch helps discharge the output. If the EN pin is toggled low then high, the switching regulator shuts down and remains off until the output voltage decays to 1.25V. At this point, the MAX16955 turns on using the soft-start sequence.
Fixed 5V Linear Regulator (BIAS)
The MAX16955 has an internal 5V linear regulator to provide its own 5V bias from a high-voltage input supply at SUP. This bias supply powers the gate drivers for the external n-channel MOSFETs and provides the power required for the analog controller, reference, and logic blocks. The bias rail needs to be stabilized by a 1F or greater capacitance at BIAS, and can provide up to 50mA (typ) total current. The linear regulator has an overcurrent threshold of approximately 100mA. In case of an overcurrent event, the current is limited to 100mA and the BIAS voltage starts to droop. As soon as VBIAS drops to 2.9V (typ), the LDO shuts down and the power MOSFETs are turned off.
Supply Voltage Range (SUP)
The supply voltage range (VSUP) of the MAX16955 is compatible to the typical automotive battery voltage range from 3.5V to 36V and can tolerate up to 42V transients. If an external 5V rail is available, use this rail to power the MAX16955 to increase efficiency by bypassing the internal LDO. Connect both BIAS and SUP to this rail, while connecting the half-bridge rectifier to the battery.
Slow Ramp-Up of the Input Voltage
If the input voltage (VSUP) ramps up slowly, the device operates in dropout mode until VSUP is greater than the regulated output voltage. The dropout mode is detected by monitoring high-side FET on for eight clock cycles. Once dropout mode is detected, the controller issues a forced low-side pulse at the rising edge of switching clock to refresh BST capacitor. This maintains the proper BST voltage to turn on the high-side MOSFET when the device is in dropout mode.
Oscillator Frequency and External Synchronization
The MAX16955 provides an internal oscillator adjustable from 220kHz to 1MHz. To set the switching frequency, connect a resistor from FOSC to SGND. See the Setting the Switching Frequency section. The MAX16955 can also be synchronized to an external clock by connecting the external clock signal to FSYNC. For proper frequency synchronization, FSYNC's input frequency must be at least 10% higher than the programmed internal oscillator frequency. A rising clock edge on FSYNC is interpreted as a synchronization input. If the FSYNC signal is lost, the internal oscillator takes control of the switching rate, returning to the switching frequency set by the resistor connected to FOSC. This maintains output regulation even with intermittent FSYNC signals. The maximum synchronizable frequency is 1.1MHz. When FSYNC is connected to SGND, the device operates in skip mode. When FSYNC is connected to BIAS
System Enable (EN) and Soft-Start
An enable control input (EN) activates the MAX16955 from its low-power shutdown mode. EN is compatible with inputs from automotive battery level down to 3.5V. The high-voltage compatibility allows EN to be connected to SUP, KEY/KL30, or the inhibit pin (INH) of a CAN transceiver. A logic-high at EN turns on the internal regulator. Once VBIAS is above the internal lockout level, VUVL = 3.1V
12
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36V, 1MHz Step-Down Controller with Low Operating Current
or driven by an external clock, the MAX16955 operates in skip mode during soft-start and transitions to fixedfrequency PWM mode after soft-start is over. threshold. The PGOOD output is open drain and should be pulled up with an external resistor to the supply voltage of the logic input it drives. This voltage should not exceed 6V. A 10k pullup resistor works well in most applications. PGOOD can sink up to 4mA of current while low. PGOOD asserts low during the following conditions: * Standby mode * Undervoltage with VOUT below 90% (typ) its set value * Overvoltage with VOUT above 111% (typ) its set value
MAX16955
Error Detection and Fault Behavior
Several error-detection mechanisms prevent damage to the MAX16955 and the application circuit: * * * * * Overcurrent protection Output overvoltage protection Undervoltage lockout at BIAS Power-good detection of the output voltage Overtemperature protection of the IC
Overcurrent Protection The MAX16955 provides cycle-by-cycle current limiting as long as the FB voltage is greater than 0.7V (i.e., 70% of the regulated output voltage). If the output voltage drops below 70% of the regulation point due to overcurrent event, 16 consecutive current-limit events initiate restart. If the overcurrent is still present during restart, the MAX16955 shuts down and initiates restart. This automatic restart continues until the overcurrent condition disappears. If the overcurrent condition disappears at any restart attempt, the device enters the normal soft-start routine. If the output is shorted through a long wire, output voltage can fall significantly below ground before reaching the overcurrent limit. Under this condition, the MAX16955 stops switching and initiates restart as soon as output drops to 20% of its regulation point. Output Overvoltage Protection The MAX16955 features an internal output overvoltage protection. If VOUT increases by 13% (typ) of the intended regulation voltage, the high-side MOSFET turns off and the low-side MOSFET turns on. The low-side MOSFET stays on until VOUT goes back into regulation. Once VOUT is in regulation, the normal switching cycles continue. Undervoltage Lockout (UVLO) The BIAS input undervoltage lockout (UVLO) circuitry inhibits switching if the 5V bias supply (BIAS) is below its UVLO threshold, 3.1V (typ). If the BIAS voltage drops below the UVLO threshold, the controller stops switching and turns off both high-side and low-side gate drivers until the BIAS voltage recovers. Power-Good Detection (PGOOD) The MAX16955 includes a power-good comparator with added hysteresis to monitor the step-down controller's output voltage and detect the power-good
The power-good levels are measured at FB if a feedback divider is used. If the MAX16955 is used in 5V mode with FB connected to BIAS, OUT is used as a feedback path for voltage regulation and power-good determination.
Overtemperature Protection Thermal-overload protection limits total power dissipation in the MAX16955. When the junction temperature exceeds +175C (typ), an internal thermal sensor shuts down the step-down controller, allowing the IC to cool. The thermal sensor turns on the IC again after the junction temperature cools by 15C and the output voltage has dropped below 1.25V (typ). A continuous overtemperature condition can cause on-/off-cycling of the device.
Fixed-Frequency, Current-Mode PWM Controller
The MAX16955's step-down controller uses a PWM, current-mode control scheme. An internal transconductance amplifier establishes an integrated error voltage. The heart of the PWM controller is an open-loop comparator that compares the integrated voltage-feedback signal against the amplified current-sense signal plus the slope compensation ramp, which are summed into the main PWM comparator to preserve inner-loop stability and eliminate inductor stair casing. At each falling edge of the internal clock, the high-side MOSFET turns on until the PWM comparator trips, the maximum duty cycle is reached, or the peak current limit is reached. During this on-time, current ramps up through the inductor, storing energy in its magnetic field and sourcing current to the output. The current-mode feedback system regulates the peak inductor current as a function of the output-voltage error signal. The circuit acts as a switch-mode transconductance amplifier and eliminates the influence of the output LC filter double pole.
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13
36V, 1MHz Step-Down Controller with Low Operating Current
During the second half of the cycle, the high-side MOSFET turns off and the low-side MOSFET turns on. The inductor releases the stored energy as the current ramps down, providing current to the output. The output capacitor stores charge when the inductor current exceeds the required load current and discharges when the inductor current is lower, smoothing the voltage across the load. Under soft-overload conditions, when the peak inductor current exceeds the selected current limit, the high-side MOSFET is turned off immediately. The low-side MOSFET is turned on and remains on to let the inductor current ramp down until the next clock cycle. sense voltage exceeds the idle-mode current-sense threshold (VCS,IDLE). See Figure 1. Under light-load conditions, the on-time duration depends solely on the skip-mode current-sense threshold, which is 25mV (typ). This forces the controller to source a minimum amount of power with each cycle. To avoid overcharging the output, another on-time cannot begin until the output voltage drops below the feedback threshold. Because the zero-crossing comparator prevents the switching regulator from sinking current, the controller must skip pulses. Therefore, the controller regulates the valley of the output ripple under light-load conditions.
MAX16955
Forced Fixed-Frequency PWM Mode
The low-noise forced fixed-frequency PWM mode (FSYNC connected to BIAS or an external clock) disables the zero-crossing comparator, which controls the low-side switch on-time. This forces the low-side gatedriver waveform to constantly be the complement of the high-side gate-drive waveform. The inductor current reverses at light loads while DH maintains a duty factor of VOUT/VSUP. The benefit of forced fixed-frequency PWM mode is to keep the switching frequency fairly constant. However, forced fixed-frequency PWM operation comes at a cost: the no-load 5V supply current can be up to 45mA, depending on the external MOSFETs and switching frequency. Forced fixed-frequency PWM mode is most useful for avoiding audio frequency noises and improving load-transient response.
Automatic Pulse-Skipping Crossover In skip mode, an inherent automatic switchover to pulse frequency modulation (PFM) takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing comparator senses the inductor current across CS to OUT. Once (VCS - VOUT) drops below the 6mV zero-crossing, current-sense threshold, the comparator forces DL low. This mechanism causes the threshold between pulseskipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). The load-current level at which PFM/PWM crossover occurs, ILOAD(SKIP), is given by:
ILOAD (SKIP) [ A ] =
Light-Load Low-Quiescent Operating (Skip) Mode
The MAX16955 includes a light-load operating mode control input (FSYNC = SGND) used to enable or disable the zero-crossing comparator. When the zerocrossing comparator is enabled, the regulator forces DL low when the current-sense inputs detect zero inductor current. This keeps the inductor from discharging the output capacitor and forces the regulator to skip pulses under light-load conditions to avoid overcharging the output. The lowest operating currents can be achieved in skip mode. When the MAX16955 operates in skip mode with no external load current, the overall current consumption can be as low as 50A. A disadvantage of skip mode is that the operating frequency is not fixed.
(VSUP - VOUT ) VOUT 2 x VSUP x fSW [MHz ] x L [H]
The switching waveforms can appear noisy and asynchronous when light-loading causes pulse-skipping operation. This is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency is made by varying the inductor value. Generally, low inductor values produce a broader efficiency versus load current, while higher values result in higher full-load efficiency (assuming that the coil resistance remains constant) and less output-voltage ripple. Drawbacks of using higher inductor values include larger physical size and degraded loadtransient response (especially at low input-voltage levels).
MOSFET Gate Drivers (DH and DL)
The DH and DL drivers are optimized for driving logiclevel n-channel power MOSFETs. The DH high-side n-channel MOSFET driver is powered by charge pumping at BST, while the DL synchronous rectifier drivers are powered directly by the 5V linear regulator (BIAS).
Skip-Mode Current-Sense Threshold When skip mode is enabled, the on-time of the stepdown controller terminates when the output voltage exceeds the feedback threshold and when the current14
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36V, 1MHz Step-Down Controller with Low Operating Current
ensures that fast-rising LX edges do not pull up the low-side MOSFET's gate, causing shoot-through currents. The capacitive coupling between LX and DL created by the MOSFET's gate-to-drain capacitance (CGD = CRSS), gate-to-source capacitance (CGS = CISS C GD ), and additional board parasitic should not exceed the following minimum threshold:
IPK
MAX16955
tON(SKIP) =
VOUT VSUPfSW
INDUCTOR CURRENT
C VGS(TH) > VSUP RSS CISS
ILOAD = IPK/2
High-Side Gate-Drive Supply (BST)
The high-side MOSFET is turned on by closing an internal switch between BST and DH. This provides the necessary gate-to-source voltage to turn on the highside MOSFET, an action that boosts the gate-drive signal above VSUP. The boost capacitor connected between BST and LX holds up the voltage across the floating gate driver during the high-side MOSFET on-time. The charge lost by the boost capacitor for delivering the gate charge is refreshed when the high-side MOSFET is turned off and the LX node swings down to ground. When the LX node is low, an internal highvoltage switch connected between BIAS and BST recharges the boost capacitor to the BIAS voltage. See the Boost-Flying Capacitor Selection section to choose the right size of the boost capacitor.
0 ON-TIME
TIME
Figure 1. Pulse-Skipping/Discontinuous Crossover Point
An adaptive dead-time circuit monitors the DH and DL outputs and prevents the opposite-side MOSFET from turning on until the other MOSFET is fully off. Thus, the circuit allows the high-side driver to turn on only when the DL gate driver has been turned off. Similarly, it prevents the low-side (DL) from turning on until the DH gate driver has been turned off. The adaptive driver dead-time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be a low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates for the adaptive deadtime circuits to work properly. Otherwise, because of the stray impedance in the gate discharge path, the sense circuitry could interpret the MOSFET gates as off while the VGS of the MOSFET is still high. To minimize stray impedance, use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the controller). Synchronous rectification reduces conduction losses in the rectifier by replacing the normal low-side Schottky catch diode with a low-resistance MOSFET switch. The internal pulldown transistor that drives DL low is robust, with a 1.6 (typ) on-resistance. This low onresistance helps prevent DL from being pulled up during the fast rise time of the LX node, due to capacitive coupling from the drain to the gate of the low-side synchronous rectifier MOSFET. Applications with high input voltages and long-inductive driver traces can require additional gate-to-source capacitance. This
Dropout Behavior During Undervoltage Transition The controller generates a low-side pulse every four clock cycles to refresh the BST capacitor during lowdropout operation. This guarantees that the MAX16955 operates in dropout mode during undervoltage transients like cold crank.
Current Limiting and Current-Sense Inputs (CS and OUT)
The current-limit circuit uses differential current-sense inputs (CS and OUT) to limit the peak inductor current. If the magnitude of the current-sense signal exceeds the current-limit threshold, the PWM controller turns off the high-side MOSFET. The actual maximum load current is less than the peak current-limit threshold by an amount equal to half the inductor ripple current. Therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and duty cycle (V OUT /V SUP ). See the Current Sensing section.
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15
36V, 1MHz Step-Down Controller with Low Operating Current MAX16955
Design Procedure
Effective Input Voltage Range
Although the MAX16955 controller can operate from input supplies up to 42V and regulate down to 1V, the minimum voltage conversion ratio (VOUT/VSUP) might be limited by the minimum controllable on-time. For proper fixed-frequency PWM operation, the voltage conversion ratio should obey the following condition: VOUT > tON(MIN) x fSW VSUP where tON(MIN) is 80ns and fSW is the switching frequency in Hz. If the desired voltage conversion does not meet the above condition, then pulse skipping occurs to decrease the effective duty cycle. To avoid this, decrease the switching frequency or lower the input voltage (VSUP).
MAX16955
OUT
RFB1 FB RFB2
Figure 2. Adjustable Output Voltage
Setting the Output Voltage
MAX16955 toc07
Connect FB to BIAS to enable the fixed step-down controller output voltage (5V), set by a preset, internal resistive voltage-divider connected between the output (OUT) and SGND.
FREQUENCY (kHz)
SWITCHING FREQUENCY vs. RFOSC
1200 1150 1100 1050 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 RFOSC (kI)
To achieve other output voltages between 1V to 13V, connect a resistive divider from OUT to FB to SGND (Figure 2). Select RFB2 (FB to SGND resistor) less than or equal to 100k. Calculate RFB1 (OUT to FB resistor) with the following equation: V RFB1 = RFB2 OUT - 1 VFB where VFB = 1V (typ) (see the Electrical Characteristics table) and VOUT can range from 1V to 13V.
25 35 45 55 65 75 85 95 105 115 125 135 145
Setting the Switching Frequency
The switching frequency, f SW , is set by a resistor (RFOSC) connected from FOSC to SGND. See Figure 3 to select the correct R FOSC value for the desired switching frequency. For example, a 400kHz switching frequency is set with RFOSC = 76.8k. Higher frequencies allow designs with lower inductor values and less output capacitance. Consequently, peak currents and I2R losses are lower at higher switching frequencies, but core losses, gatecharge currents, and switching losses increase.
Figure 3. Switching Frequency vs. RFOSC
peak-to-peak AC current to DC average current (LIR) must be selected first. A good compromise between size and loss is a 30% peak-to-peak ripple current to average-current ratio (LIR = 0.3). The switching frequency, input voltage, output voltage, and selected LIR then determine the inductor value as follows: L= VOUT VSUP(MIN) - VOUT
Inductor Selection
Three key inductor parameters must be specified for operation with the MAX16955: inductance value (L), inductor saturation current (ISAT), and DC resistance (RDCR). To select inductance value, the ratio of inductor
16
VSUP(MIN) x fSW x IOUT(MAX) x LIR
(
)
where VSUP(MIN) is the minimum supply voltage, VOUT is the typical output voltage, and IOUT(MAX) is the maximum
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36V, 1MHz Step-Down Controller with Low Operating Current
load current. The switching frequency is set by RFOSC (see the Setting the Switching Frequency section). The MAX16955 uses internal frequency independent slope compensation to ensure stable operation at duty cycles above 50%. The maximum slope compensation ramp voltage over a full clock period is 200mV. Use the equation below to select the inductor value: VOUT [V] = 1 25% L[H] x fSW [MHz] However, if it is necessary, higher inductor values can be selected. The exact inductor value is not critical and can be adjusted to make trade-offs among size, cost, efficiency, and transient response requirements. Table 1 shows a comparison between small and large inductor sizes. The core must be large enough not to saturate at the peak inductor current (IPEAK): IPEAK = ILOAD(MAX) + IINDUCTOR 2
MAX16955
Transient Response
The inductor ripple current also impacts transient response performance, especially at low VSUP - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The total output voltage sag is the sum of the voltage sag while the inductor is ramping up and the voltage sag before the next pulse can occur:
VSAG = L ILOAD(MAX) ILOAD(MAX) ( t - t ) + COUT 2COUT (( VSUP x DMAX ) - VOUT )
(
)
2
Table 1. Inductor Size Comparison
INDUCTOR SIZE SMALLER Lower price Smaller form factor Faster load response LARGER Smaller ripple Higher efficiency Larger fixed-frequency range in skip mode
where D MAX is the maximum duty factor (see the Electrical Characteristics table), L is the inductor value in H, COUT is the output capacitor value in F, t is the switching period (1/fSW) in s, and t equals (VOUT/VSUP) x t when in fixed-frequency PWM mode, or L x 0.2 x IMAX/(VSUP - VOUT) when in skip mode. The amount of overshoot (VSOAR) during a full-load to noload transient due to stored inductor energy can be calculated as: VSOAR
The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 25% and 45% ripple current. When pulse skipping (FSYNC low and light loads), the inductor value also determines the load-current value at which PFM/PWM switchover occurs. For the selected inductance value, the actual peak-topeak inductor ripple current (IINDUCTOR) is defined by: IINDUCTOR = VOUT ( VSUP - VOUT ) VSUP x fSW x L
(ILOAD(MAX) )
2
L
2COUT VOUT
Current Sensing
For the most accurate current sensing, use a currentsense resistor (RSENSE) between the inductor and the output capacitor. Connect CS to the inductor side of R SENSE, and OUT to the capacitor side. Dimension RSENSE so its maximum current (IOC) induces a voltage of VLIMIT (72mV minimum) across RSENSE. If a higher voltage drop across RSENSE must be tolerated, divide the voltage across the sense resistor with a voltage-divider between CS and OUT to reach VLIMIT (72mV minimum). The current-sense method (Figure 4) and magnitude determine the achievable current-limit accuracy and power loss. Typically, higher current-sense limits provide tighter accuracy, but also dissipate more power. For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor with low parasitic inductance between the inductor and output as shown in Figure 4a.
17
where IINDUCTOR is in mA, L is in H, and fSW is in kHz.
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36V, 1MHz Step-Down Controller with Low Operating Current MAX16955
Alternatively, high-power applications that do not require highly accurate current-limit protection can reduce the overall power dissipation by connecting a series RC circuit across the inductor (Figure 4b) with an equivalent time constant: R2 RCSHL = R R1 + R2 DCR and: RDCR = L 1 1 + CEQ R1 R2 where RCSHL is the required current-sense resistor and RDCR is the inductor's series DC resistance. Use the typical inductance and RDCR values provided by the inductor manufacturer. Carefully observe the PCB layout guidelines to ensure the noise and DC errors do not corrupt the differential current-sense signals seen by CS and OUT. Place the sense resistor close to the IC with short, direct traces, making a Kelvin-sense connection to the current-sense resistor.
INPUT (VIN) CIN
MAX16955
DH LX DL GND CS OUT a) OUTPUT SERIES RESISTOR SENSING NL DL COUT NH L RSENSE
INPUT (VIN) CIN
MAX16955
DH LX DL GND CS OUT b) LOSSLESS INDUCTOR SENSING CEQ NL DL R1 R2 COUT RCSHL = RDCR = NH L INDUCTOR RDCR
(
R2 RDCR R1 + R2
)
L CEQ
[
1 1 + R1 R2
]
Figure 4. Current-Sense Configurations
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36V, 1MHz Step-Down Controller with Low Operating Current
Input Capacitor
The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit's switching. The input capacitor RMS current requirement (IRMS) is defined by the following equation: IRMS = ILOAD(MAX) VOUT ( VSUP - VOUT ) VSUP absorb the inductor energy while transitioning from fullload to no-load conditions without tripping the overvoltage fault protection. When using high-capacitance, low-ESR capacitors, the filter capacitor's ESR dominates the output-voltage ripple. The size of the output capacitor depends on the maximum ESR required to meet the output-voltage ripple (VRIPPLE(P-P)) specifications: VRIPPLE(P -P) = ESR x ILOAD(MAX) x LIR In skip mode, the inductor current becomes discontinuous, with the peak current set by the skip-mode current-sense threshold (VSKIP = 32mV, typ). In skip mode, the no-load output ripple can be determined as follows: V x ESR VRIPPLE(P -P) = SKIP RSENSE The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value. When using low-value filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, low-value filter capacitors typically have high-ESR zeros that can affect the overall stability.
MAX16955
I RMS has a maximum value when the input voltage equals twice the output voltage (VSUP = 2VOUT), so IRMS(MAX) = ILOAD(MAX)/2. Choose an input capacitor that exhibits less than +10C self-heating temperature rise at the RMS input current for optimal long-term reliability. The input-voltage ripple comprises VQ (caused by the capacitor discharge) and VESR (caused by the ESR of the capacitor). Use low-ESR ceramic capacitors with high-ripple-current capability at the input. Assume the contribution from the ESR and capacitor discharge is equal to 50%. Calculate the input capacitance and ESR required for a specified input voltage ripple using the following equations: ESRIN = VESR I IOUT + L 2
where: IL = and: I x D (1 - D) CIN = OUT VQ x fSW where: V D = OUT VSUP
( VSUP - VOUT ) x VOUT
VSUP x fSW x L
Compensation Design
The MAX16955 uses an internal transconductance error amplifier with its inverting input and its output available to the user for external frequency compensation. The output capacitor and compensation network determine the loop stability. The inductor and the output capacitor are chosen based on performance, size, and cost. Additionally, the compensation network optimizes the control-loop stability. The controller uses a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor. The MAX16955 uses the voltage drop across the DC resistance of the inductor or the alternate series current-sense resistor to measure the inductor current. Current-mode control
Output Capacitor
The output filter capacitor must have low enough ESR to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. The output capacitance must be high enough to
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36V, 1MHz Step-Down Controller with Low Operating Current
eliminates the double pole in the feedback loop caused by the inductor and output capacitor, resulting in a smaller phase shift and requiring less elaborate erroramplifier compensation than voltage-mode control. A simple single-series resistor (RC) and capacitor (CC) are required to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for output filtering (Figure 5). For other types of capacitors, due to the higher capacitance and ESR, the frequency of the zero created by the capacitance and ESR is lower than the desired closed-loop crossover frequency. To stabilize a nonceramic output capacitor loop, add another compensation capacitor (CF) from COMP to SGND to cancel this ESR zero. The basic regulator loop is modeled as a power modulator, output feedback divider, and an error amplifier. The power modulator has a DC gain set by g mc x RLOAD, with a pole and zero pair set by RLOAD, the output capacitor (COUT), and its ESR. The following equations determine the approximate value for the gain of the power modulator (GAINMOD(dc)), neglecting the effect of the ramp stabilization. Ramp stabilization is necessary when the duty cycle is above 50% and is internally and automatically done for the MAX16955: GAINMOD(dc) gmc x RLOAD x fSW x L RLOAD + ( fSW x L )
MAX16955
The feedback voltage-divider has a gain of GAINFB = VFB/VOUT, where VFB is 1V (typ). The transconductance error amplifier has a DC gain of GAINEA(dc) = gm,EA x ROUT,EA, where gm,EA is the error amplifier transconductance, and ROUT,EA is the output resistance of the error amplifier. Use gm,EA of 2500S (max) and ROUT,EA of 30M (typ) for compensation design with the highest phase margin. A dominant pole (fdpEA) is set by the compensation capacitor (CC), the compensation resistor (RC), and the amplifier output resistance (ROUT,EA). A zero (fzEA) is set by the compensation resistor (RC) and the compensation capacitor (CC). There is an optional pole (fpEA) set by CF and RC to cancel the output capacitor ESR zero if it occurs near the crossover frequency (f C , where the loop gain equals 1 (0dB)). Thus: fdpEA = 1 2 x CC x (ROUT,EA + RC ) 1 2 x CC x RC 1 2 x CF x RC
fzEA =
where RLOAD = VOUT/IOUT(MAX) in , fSW is the switching frequency in MHz, L is the output inductance in H, and gmc = 1/(AV_CS x RDC) in S. AV_CS is the voltage gain of the current-sense amplifier and is typically 11V/V (see the Electrical Characteristics table). RDC is the DC-resistance of the inductor or the current-sense resistor in . In a current-mode step-down converter, the output capacitor, its ESR, and the load resistance introduce a pole at the following frequency: 1 fpMOD = R x f xL 2 x COUT x LOAD SW + ESR R LOAD + ( fSW x L ) The output capacitor and its ESR also introduce a zero at: fzMOD = 1 2 x ESR x COUT
fpEA =
The loop-gain crossover frequency (fC) should be set below 1/5 the switching frequency and much higher than the power-modulator pole (fpMOD): f fpMOD << fC SW 5 The total loop gain as the product of the modulator gain, the feedback voltage-divider gain, and the error amplifier gain at fC should be equal to 1. So: GAINMOD( fC) x VFB x GAINEA( fC) = 1 VOUT
For the case where fzMOD is greater than fC: GAINEA( fC) = gm,EA x RC GAINMOD( fC) = GAINMOD(dc) x fpMOD fC
When COUT is composed of n identical capacitors in parallel, the resulting COUT = n x COUT(EACH), and ESR = ESR(EACH)/n. Note that the capacitor zero for a parallel combination of like capacitors is the same as for an individual capacitor.
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36V, 1MHz Step-Down Controller with Low Operating Current
Therefore: GAINMOD( fC) x Solving for RC: RC = VOUT gm,EA x VFB x GAINMOD( fC) VFB x gm,EA x RC = 1 VOUT Solving for RC: RC = VOUT x fC gm,EA x VFB x GAINMOD( fC) x fzMOD
MAX16955
Set the error-amplifier compensation zero formed by RC and CC at the fpMOD (fzEA = fpMOD): CC = 1 2 x f2MOD x RC
Set the error-amplifier compensation zero formed by RC and CC (fzEA) at the fpMOD. Calculate the value of CC as follows: CC = 1 2 x fpMOD x RC
If fzMOD is less than 5 x fC, add a second capacitor CF from COMP to SGND. Set fpEA = fzMOD and calculate CF as follows: CF = 1 2 x RC x fzMOD
If fzMOD is less than 5 x fC, add a second capacitor, CF, from COMP to SGND and set the compensation pole formed by R C and C F (f pEA ) at the f zMOD . Calculate the value of CF as follows: CF = 1 2 x fzMOD x RC
MOSFET Selection
The MAX16955's controller drives two external logiclevel n-channel MOSFETs as the circuit switch elements. The key selection parameters to choose these MOSFETs include: * * * * * * On-resistance (RDS(ON)) Maximum drain-to-source voltage (VDS(MAX)) Minimum threshold voltage (VTH(MIN)) Total gate charge (QG) Reverse-transfer capacitance (CRSS) Power dissipation
As the load current decreases, the modulator pole also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same. For the case where fzMOD is less than fC: The power-modulator gain at fC is: GAINMOD( fC) = GAINMOD(dc) x The error-amplifier gain at fC is: f GAINEA( fC) = gm,EA x RC x zMOD fC Therefore: fpMOD fzMOD
VOUT R1
R2 VREF
gm
COMP
RC
CC
CF
f V GAINMOD( fC) x FB x gm,EA x RC x zMOD = 1 VOUT fC
Figure 5. Compensation Network
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36V, 1MHz Step-Down Controller with Low Operating Current
Both n-channel MOSFETs must be logic-level types with guaranteed on-resistance specifications at VGS = 4.5V. Ensure that the conduction losses at minimum input voltage do not exceed MOSFET package thermal limits or violate the overall thermal budget. Also, ensure that the conduction losses, plus switching losses at the maximum input voltage, do not exceed package ratings or violate the overall thermal budget. The MAX16955's DL gate driver must drive the low-side MOSFET (NL). In particular, check that the dV/dt caused by the high-side MOSFET (NH) turning on does not pull up the NL gate through its drain-to-gate capacitance. This is the most frequent cause of cross-conduction problems. Gate-charge losses are dissipated by the driver and do not heat the MOSFET. Therefore, if the drive current is taken from the internal LDO regulator, the power dissipation due to drive losses must be checked. Both MOSFETs must be selected so that their total gate charge is low enough; therefore, BIAS can power both drivers without overheating the IC: PDRIVE = (VSUP - VBIAS) x QG_TOTAL x fSW where QG_TOTAL is the sum of the gate charges of both MOSFETs.
MAX16955
Should this value be lower than the ideal capacitance and assuming that the minimum bootstrap capacitor should be large enough to supply 2V (typ) effective gate voltage: CBST(MIN) = QG VBIAS(MIN) - VTH(TYP) - 2V
Should the minimum value still be too large to be recharged sufficiently, a parallel bootstrap Schottky diode may be necessary.
Power Dissipation
The MAX16955's maximum power dissipation depends on the thermal resistance from the die to the ambient environment and the ambient temperature. The thermal resistance depends on the device package, PCB copper area, other thermal mass, and airflow. The device's power dissipation depends on the internal linear regulator current consumption (PLIN) and the dynamic gate current (PGATE): PT = PLIN + PGATE Linear power is the average bias current times the voltage drop from VSUP to VBIAS: PLIN = IBIAS,AV x (VSUP - VBIAS) where I BIAS,AV = I SUP(MAX) + f SW x (Q G_DH(MAX) + QG_DL(MAX)), ISUP(MAX) is 2mA, fSW is the switching frequency programmed at FOSC, and QG_ is the MOSFET data sheet's total gate-charge specification limits at VGS = 5V. Dynamic power is the average power during charging and discharging of both the external gates per period of oscillation: PGATE = 2 x where: 2x V 2BIAS W x tG,RISE 0.2 x10-6 RHS / LS Hz V 2BIAS x tG,RISE x fSW RHS / LS
Boost-Flying Capacitor Selection
The bootstrap capacitor stores the gate voltage for the internal switch. Its size is constrained by the switching frequency and the gate charge of the high-side MOSFET. Ideally the bootstrap capacitance should be at least nine times the gate capacitance: CBST(TYP) = 9 x QG VBIAS
This results in a 10% voltage drop when the gate is driven. However, if this value becomes too large to be recharged during the minimum off-time, a smaller capacitor must be chosen. During recharge, the internal bootstrap switch acts as a resistor, resulting in an RC circuit with the associated time constants. Two s (time constants) are necessary to charge from 90% to 99%. The maximum allowable capacitance is, therefore: CBST(MAX) = tOFF(MIN) 2 x RBST(MAX)
When in dropout, tOFF(MIN) is the minimum on-time of the low-side switch and is approximately half the clock period. When not in dropout, tOFF(MIN) = 1 - DMAX.
is the frequency-dependent power, dissipated during one turn-on and turn-off cycle of each of the external n-channel MOSFETs. RHS/LS is the on-resistance of the NH and NL.
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36V, 1MHz Step-Down Controller with Low Operating Current
To estimate the temperature rise of the die, use the following equation: TJ = TA + (PT x JA) where JA is the junction-to-ambient thermal resistance of the package, PT is power dissipated in the device, and TA is the ambient temperature. The JA is 38.3C/W for the 16-pin TSSOP package on multilayer boards, with the conditions specified by the respective JEDEC standards (JESD51-5, JESD51-7). If actual operating conditions significantly deviate from those described in the JEDEC standards, then an accurate estimation of the junction temperature requires a direct measurement of the case temperature (TC). Then, the junction temperature can be calculated using the following equation: TJ = TC + (PT x JC) Use 3C/W as JC thermal resistance for the 16-pin TSSOP package. The case-to-ambient thermal resistance (CA) is dependent on how well the heat is transferred from the PCB to the ambient. Therefore, solder the exposed pad of the TSSOP package to a large copper area to spread heat through the board surface, minimizing the case-to-ambient thermal resistance. Use large copper areas to keep the PCB temperature low. If possible, place all power components on the top side of the board and run the power stage currents, especially large high-frequency components, using traces or copper fills on the top side only, without adding vias. On the top side, lay out a large PGND copper area for the output, and connect the bottom terminals of the high-frequency input capacitors, output capacitors, and the source terminals of the low-side MOSFET to that area. Then, make a star connection of the SGND plane to the top copper PGND area with few vias in the vicinity of the source terminal sensing. Do not connect PGND and SGND anywhere else. Refer to the MAX16955 evaluation kit data sheet for guidance. Keep the power traces and load connections short, especially at the ground terminals. This practice is essential for high efficiency and jitter-free operation. Use thick copper PCBs (2oz. vs. 1oz.) to enhance efficiency. Place the controller IC adjacent to the synchronous rectifier MOSFET (NL) and keep the connections for LX, PGND, DH, and DL short and wide. Use multiple small vias to route these signals from the top to the bottom side. The gate current traces must be short and wide, measuring 50 mils to 100 mils wide if the low-side MOSFET is 1in from the controller IC. Connect the PGND trace from the IC close to the source terminal of the low-side MOSFET. Route high-speed switching nodes (BST, LX, DH, and DL) away from the sensitive analog areas (FOSC, COMP, and FB). Group all SGND-referred and feedback components close to the IC. Keep the FB and compensation network nets as small as possible to prevent noise pickup.
MAX16955
Applications Information
PCB Layout Guidelines
Make the controller ground connections as follows: create a small analog ground plane near the IC by using any of the PCB layers. Connect this plane to SGND and use this plane for the ground connection for the SUP bypass capacitor, compensation components, feedback dividers, and FOSC resistor.
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23
36V, 1MHz Step-Down Controller with Low Operating Current MAX16955
VBAT 5.5V TO 28V
D1 C1 C2 C3 1 SUP 2 EN BST R2 VL_IN D2 RED 10 PGOOD LX DL PGND 4 C9 R4 FSYNC CS 3 5 FOSC SGND BIAS 13 FB 7 OUT 9 C6 C5 8 R3 VOUT 5V
R1 VEN
DH
15 16 14 12 11 C4
N1-B
L1
MAX16955
6
COMP
N1-A
R5
C8
C7
Figure 6. Typical Operating Circuit for VOUT = 5V
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36V, 1MHz Step-Down Controller with Low Operating Current MAX16955
VBAT 5.5V TO 28V C1 C2 C3 1 SUP 2 EN BST R7 *VBIAS D1 6 R6 C8 R5 COMP 10 PGOOD LX DL PGND 4 3 5
R4 VEN
DH
15 16 14 12 11 C4
N1-B
L1
MAX16955
N1-A
C9
FSYNC FOSC SGND BIAS 13 C7 FB 7
CS
8 R3
OUT
9 R1 C5 C6
VOUT 1.2V/5A
R2
*CONNECT FSYNC TO BIAS FOR FIXED-FREQUENCY PWM MODE. CONNECT FSYNC TO SGND FOR SKIP MODE.
Figure 7. Typical Operating Circuit for Adjustable Output Voltage, VOUT = 1.2V/5A
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 16 TSSOP-EP PACKAGE CODE U16E+3 OUTLINE NO. 21-0108 LAND PATTERN NO. 90-0120
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25
36V, 1MHz Step-Down Controller with Low Operating Current MAX16955
Revision History
REVISION NUMBER 0 REVISION DATE 3/11 Initial release DESCRIPTION PAGES CHANGED --
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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